This invention relates to a layer of titanium-tungsten (TiW) used as a diffusion barrier in a low metal resistance ohmic contact alloyed to p type indium phosphide (p InP) semiconductor material.
This invention relates more particularly to the fabrication of a low metal resistance ohmic contact through the use of TiW as a diffusion barrier layer between an underlay of AnZn contact layer alloyed to p InP and an overlay of suitable metal, especially Au.
This invention relates in particular to a layer of TiW used as a diffusion barrier in a AuZn/TiW/Au layered ohmic contact alloyed to p InP material of a semiconductor device, and especially relates to the same where the ohmic contact serves as the gate contact of an InP junction field effect transistor (JFET) having gate, source, channel and drain regions and ohmic contacts to the gate, source and drain.
This invention relates more particularly to a technique that prevents degradation of the gate metal resistance of an ohmic gate contact of an InP junction FET.
Prior art pertinent to the present invention is set forth in an article entitled, "Low-Resistance Ohmic Contacts to p InP", by C. L. Cheng et al., appearing in Electronics Letters, Vol. 18, No. 17, August 1982. This article, however, does not teach that TiW material can be used as a diffusion barrier layer in an ohmic contact to p InP.
Parasitic gate metal resistance plays a major role in determining the ultimate performance characteristics of microwave FETs. Junction FET structures are especially sensitive to gate resistance since (1) there is an additional p-type ohmic contact resistance not present in conventional MESFET structures and (2) the gate metal resistance itself generally increases to several time its bulk value (prior to alloying) as a result of the high temperature alloy process needed and used to form the associated p-type ohmic contact.
The metallization sequence which is commonly used for the formation of the p+ ohmic contact to the p+n junction gate of an InP JFET is evaporated AuZn (90%:10% by weight) with an overlayer of evaporated Au. To obtain a low ohmic gate metal resistance, this two layer metallization must subsequently be alloyed at a temperature above 400.degree. C. The Au gate metal overlayer resistivity in respective test samples has been observed to increase by at least 180% and as much as 450% as a result of this alloying cycle. The outdiffusion of Zn and/or In and P into the Au overlayer is suspect as the cause for this phenomena.
To minimize gate metal resistivity increases with alloying we use a sputtered TiW layer between the AuZn and Au layers as a diffusion barrier to Zn, In and P outdiffusion.